This invention relates to the production of multi-chip electronic modules, and more particularly to a method and apparatus for attaching multiple integrated circuit packages to printed circuit boards. It also relates to high-density memory modules having three-dimensional arrangements of integrated circuit packages.
Demand for semiconductor memory is highly elastic. When such memory is relatively inexpensive compared to the overall cost of a computer system, an almost unsatiable demand results, with computer manufacturers tending to install an amount of main memory in each system that greatly exceeds the amount required for average program use. On the other hand, when it is costly, manufacturers typically install an amount in each system that only marginally fulfills the requirement of the average program. Although the sales prices of computers may, thus, be maintained at low levels, the end user may soon find that he must upgrade his computer""s main memory.
The ever increasing demand for large random access computer memories, and the growing demand for increasingly compact computers, coupled with an incentive on the part of the semiconductor manufactureres to reduce the cost per bit, has lead to not only a quadrupling of circuit density approximately every three years, but to increasingly efficient techniques for packaging and mounting the circuit chips. Up until the late 1980""s, semiconductor memory chips were usually packaged as dual in-line pin packages (DIPPs). The pins of these DIPP packages were generally soldered directly within through-holes in a circuit board (e.g., the motherboard), or they were inserted in sockets which were, in turn, soldered within through-holes in the circuit board. With the advent of surface mount technology, conventional plated through-holes on printed circuit boards have been replace with conductive mounting pads. Small Outline J-lead (SOJ) packages have led to Thin Small Outline Packages (TSOPs). Because the pitch or spacing between centers of adjacent surface mount pins is significantly less than the conventional 0.10-inch spacing for conventional through-hole components, surface mount chips tend to be considerably smaller than corresponding conventional chips, thus taking up less space on a printed circuit board. Additionally, as through holes are no longer needed, surface mount technology lends itself to the mounting of components on both sides of a printed circuit board. Memory modules utilizing surface-mount packages on both sides have become the standard. Both the earlier single in-line memory modules (SIMMs) and the currently used dual in-line memory modules (DIMMs) are inserted into sockets on the motherboard.
Packaging density may be increased rather dramatically by fabricating modules in which a plurality of integrated circuit (IC) chips, such as memory chips, are stacked in a three dimensional arrangement. As a general rule, the three-dimensional stacking of chips requires complex, non-standard packaging methods.
One example of a vertical stack of IC chips is provided by U.S. Pat. No. 4,956,694 to Floyd Eide, titled INTEGRATED CIRCUIT CHIP STACKING. A plurality of integrated circuits are packaged within chip carriers and stacked, one on top of the other, on a printed circuit board. Except for the chip select terminal, all other like terminals on the chips are connected in parallel.
Another example of chip stacking is given in U.S. Pat. No. 5,128,831 to Fox, et al. titled HIGH-DENSITY ELECTRONIC PACKAGE COMPRISING STACKED SUB-MODULES WHICH ARE ELECTRICALLY INTERCONNECTED BY SOLDER-FILLED VIAS. The package is assembled from individually testable sub-modules, each of which has a single chip bonded thereto. The sub-modules are interleaved with frame-like spacers. Both the sub-modules and the spacers have alignable vias which provide interconnection between the various sub-modules.
U.S. Pat. No. 5,313,096, also issued to Floyd Eide and titled IC CHIP PACKAGE HAVING CHIP ATTACHED TO AND WIRE BONDED WITHIN AN OVERLYING SUBSTRATE, is another example. Such a package includes a chip having an upper active surface bonded to the lower surface of a lower substrate layer having conductive traces on its upper surface which terminate in conductive pads on its periphery. Connection between terminals on the active surface and the traces is made with wire bonds through apertures within the lower substrate layer. An upper substrate layer, which is bonded to the lower substrate layer, has apertures which coincide with those of the lower substrate layer and provide space in which the wire bonding may occur. After wire bonding has occurred, the apertures are filled with epoxy to form an individually testable sub-module. Multiple sub-modules can be stacked and interconnected with metal strips attached to their edges.
A final example of a stacked-chip module is disclosed in U.S. Pat. No. 5,869,353 to A. U. Levy, et al. titled MODULAR PANEL STACKING PROCESS. A plurality of panels are fabricated having apertures therein, an array of chip-mounting pads at the bottom of the apertures, and interfacing conductive pads. Both the chip-mounting pads and the interfacing conductive pads are coated with solder paste. Plastic-encapsulated surface-mount IC chips are positioned on the paste-covered mounting pads, multiple panels are stacked in a layered arrangement and the stack is heated to solder the chip leads to the mounting pads and the interfacing pads of adjacent panels together. Individual chip package stacks are then separated from the panel stack by a cutting and cleaving operation.
As can be seen by the foregoing examples, increased chip density is achieved through the use of complicated packaging and stacking arrangements, which must necessarily be reflected in a higher costs per bit of storage.
The present invention provides for an improved muti-chip module having increased chip density. All embodiments of the improved module include a circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes multiple IC packages, which are mounted on both opposing sides of a package carrier. The package units may be mounted on one or both sides of the circuit board.
A first embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. At least one IC package is surface mounted on each major planar surface, by interconnecting the connection elements of the package with the contact pads on the planar surface, to form the IC package unit. Each unit is mounted within its own recess in the circuit board, with one IC package being right-side up, and the other being upside-down. The upside-down IC package may be in contact with a heat sink layer embedded within the circuit board. If corresponding contact pads on both sides of the package carrier are interconnected within the carrier body, contact may be made between the connection elements, or leads, of the IC package closest to the circuit board and the interconnection pads thereon. Using this interconnection technique, the chip carrier may be either a rigid or semi-rigid laminar substrate or it may be a thin film carrier. For another variation of this first embodiment, the laminar substrate package carrier may be modified to incorporate its own set of interconnection leads which mate with the interconnection pads on the circuit board. Greater flexibility is provided by this technique, as rerouting of lead positions may take place within the carrier body. In addition, if connection elements on one IC package must be connected independently with respect to corresponding connection elements on the other package of the package pair (e.g., chip select leads), additional carrier leads may be provided to accomplish the independent connections.
A second embodiment of the invention utilizes a carrier substrate which has at least one recess on each opposing surface for back-to-back surface mounting of the IC packages. IC packages mounted on opposite sides of the carrier may be in contact with opposite sides of a heat sink layer embedded within the carrier substrate. Each resulting IC package unit is surface mounted to the circuit board. If the leads of both packages are interconnected on the carrier, then connection to the circuit board may be made by attaching the leads of only one package directly to the circuit board. However, like the first embodiment, the package carrier may be equipped with its own leads which are connected to the various leads of the mounted IC packages. In such a case, the package carrier leads are directly connected to the interconnection pads on the circuit board.
Third and fourth embodiments of the invention utilize a third embodiment IC package unit having carriers which incorporate features of both the first and second embodiments. One of the packages is mounted on a planar surface of the carrier right-side up, while the other package is mounted on the carrier in a recess upside down. Two different embodiments of modules result because the carrier may be mounted on two types of circuit boards. Either the IC package that is mounted on the planar surface of the carrier, or the IC package that is mounted within the recess, may be mounted adjacent to the circuit board. In the former case, the adjacent package of the package unit fits within a recess on the circuit board. In the latter case, the adjacent package of the package unit mounts on a planar surface of the circuit board. As in the other embodiments, the carrier may be equipped with its own set of interconnection leads which interface with the interconnection pads on the circuit board. Likewise, if the leads of one package are interconnected with those of the other package on the carrier, connection to the circuit board may be made with the leads of the adjacent package.
A fifth embodiment module utilizes a fourth embodiment IC package unit. The primary difference between the fourth embodiment carrier and third embodiment carrier is the addition of carrier leads to the former, the leads being used to attach the fourth embodiment package unit to a circuit board.
A sixth embodiment module utilizes a fifth embodiment IC package unit having a flexible thin film substrate. In most other respects, this IC package unit is similar to the first embodiment IC package unit.
A seventh embodiment module utilizes a sixth embodiment IC package unit having ball-grid-array type IC packages. Because the connection elements (the pads and attached balls) are oriented face down against the surface of the carrier, this particular package unit utilizes carrier leads to make connection to the printed circuit board.
For any of the seven module embodiments, electrical connection between electrical traces on the carrier and electrical traces on the circuit board may be accomplished using one of several commonly used interconnection techniques, such as solder reflow, solder dot bridges, or ball grid joints. In the case where the carrier itself is equipped with leads, leads of the xe2x80x9cJxe2x80x9d or gull-wing type may be used, with the latter type being the preferred.
The invention may be utilized to increase memory density on memory modules. For other types of IC packages, it may be employed to more efficiently utilize available real estate on a printed circuit board.